1. Field of the Invention
The invention relates to a method and a control device for writing data into a memory, and more particularly relates to a method and control device for preventing data from being overwritten while writing data into memory.
2. Description of the Prior Art
Memory devices, such as SRAM, DRAM, or FLASHRAM, are used in many electronic devices. With the progress of processing rate for a processing unit (such as a CPU), the processing rate for memory devices has to be increased. For instance, a multi-port system that allows different read/write operations to be done simultaneously is applied in many memory devices. However, because of the ordinary limitations for small, portable electronic devices (e.g., power consumption, volume size, or heat dissipation), many of them prefer a single-port system rather than the multi-port system to store data and signals. For example, a single-port SRAM system is widely used in the IC driver for displaying images on the LCD panel of a mobile phone.
FIG. 1 illustrates the conventional single-port SRAM system 10 that is often seen in LCD IC driver of a mobile phone or a PDA. System 10 includes the following circuit components: a SRAM controller SRAM_CTRL 100; an arbiter 102; a timing controller TIMING_CTRL 104; and a SRAM 106. Among them, SRAM 106 is provided for storing the data of an electronic device; SRAM_CTRL 100 is an access controller, which electrically communicates with the CPU and controls of the external read/write operation for the SRAM 106. The TIMING_CTRL 104 repeatedly generates control signals CS to the SRAM 106 for performing an internal read operation that outputs data (e.g., pixel bits) stored in the SRAM 106 to the source driver (LCD panel) in order to display images; and the arbiter 102 determines which operation (external write, read, and internal read) will be performed to the SRAM 106. One characteristic of the single-port SRAM system is that only one read/write operation may be performed at the same moment. In this example, the internal read operation has a higher priority than the external read/write operation. The single-port SRAM system 10 has two operational modes, called the normal mode and the high speed write mode (HWM mode) respectively, for different demands of writing speeds. Functions for each component and the detail process for two operational modes will be described below. However, the descriptions will be focused on an external write operation for adapting to the aspects of the invention.
Data on a data bus is not directly written into SRAM 106 but temporarily held in the SRAM_CTRL 100 till obtaining the write permission from the arbiter 102. FIG. 2A illustrates a diagram for the SRAM_CTRL 100, and FIG. 2B shows the relevant timing diagram as in a normal mode. In the normal mode, when the CPU wants to write data into the SRAM 106, firstly it sends an external write request E_NWR to SRAM_CTRL 100. Before writing the data into the SRAM 106, firstly the data on a data bus originally will be input into a flip-flop FF, it will then input into different latches according to a latch address L_ADDR. As shown in FIG. 2A, there are four latches named as L1, L2, L3, and L4 respectively, therefore L_ADDR needs at least two bits to identify four latches (e.g., 00 for L1, 01 for L2, 10 for L3, and 11 for L4). In general, we may choose the last two bits of a write address ADDR as L_ADDR, therefore no additional address generator is needed (or at most a register for storing the last two bits of ADDR).
Referring to FIG. 2B, when the external write request E_NWR 20 comes and goes high, the data in flip-flop FF will be inputted into the latch L1 according to L_ADDR (202). In the same time, SRAN_CTRL 100 sends a request signal EXT_WR 22 to the arbiter 102 for permission for writing data into the SRAM 106. If it's allowable to write the data into the SRAM 106, the arbiter 102 will respond by sending an acknowledge signal EXT_PULSE 24 to the SRAM_CTRL 100. As receiving the acknowledge signal EXT_PULSE 24, SRAM_CTRL 100 generates and sends a clock signal CLK 26 immediately into the SRAM 106, which triggers the SRAM 106 writing data into the proper memory addresses according to the write address ADDR. Afterward, the clock signal CLK goes low, the value of L_ADDR is increased (00 to 01) (204), so that when a new E_NWR 28 comes and goes high, the new latch address L_ADDR will indicate latch L2 for the data to be input.
With regard to the HWM mode, E_NWR comes more rapidly than in the normal mode, and there are more write requests per complete write operation. Referring to FIG. 2C, which illustrates the relevant timing diagram for the SRAM_CTRL 100 as operating in the HWM mode. In the HWM mode, a complete write operation consists of four external write requests and a clock signal. When the E_NWR goes high (230), data in the flip-flop FF is inputted into each latch by reference to an latch address HWM_ADDR, which controls the access for latches in the high speed write mode. With a delay time (e.g., 10 ns) after E_NWR goes high, the value of the HWM_ADDR will automatically be changed (00 to 01) (232), that the new latch address HWM_ADDR will be applied to indicate which latch the succeeding data will be inputted as a new E_NWR comes. The foregoing steps repeat until the value of the HWM_ADDR becomes 11 (234), which indicates to the last latch (L4) for the write operation. Then the SRAM_CTRL 100 sends the request signal EXT_WR to the arbiter 102 for the write permission. In this moment, the data and the write address of the SRAM 106 are ready. When the arbiter 102 receives the request signal EXT_WR, the arbiter 102 will respond by sending an acknowledge signal EXT_PLUSE to the SRAM_CTRL 100 if it's allowable to write data into the SRAM 106 (EXT_WR and EXT_PULSE are not shown in drawing). After receiving the acknowledge signal EXT_PLUSE, the SRAM_CTRL 100 generates and sends the clock signal CLK (236) into the SRAM 106, thereby writing the data held in latches into the proper memory addresses according to the write address ADDR. In the next procedure, as the clock signal CLK goes low, the value of the ADDR is changed (238) to indicate the memory address of the SRAM 106 for the next write operation.
As foregoing descriptions, a complete write operation is accomplished after the clock signal CLK is generated and the value of the write address ADDR is changed. No matter which operational mode it is, however, a serious problem may occur when the clock signal CLK comes too late. In some situations, the arbiter 102 may not immediately respond to the request signal EXT_WR. For example, if the TIMING_CTRL 104 also sends an internal read request INT_RD to the arbiter 102 at the same time, the arbiter 102 will respond with an acknowledge signal IN_PULSE for the internal read request INT_RD prior to the external write request EXT_WR. Therefore, the acknowledge signal EXT_PULSE will arrive late to the SRAM_CTRL 100. A delayed EXT_PLUSE will result in a delayed clock signal CLK, thereby resulting in the clock signal CLK being generated after a succeeding write request E_NWR of new write operation.
In the normal mode, referring to the timing diagram of FIG. 2D, because the value of L_ADDR changes at the moment as the clock signal CLK goes low, hence if CLK comes too late after data has been inputted into the corresponding latch (260) and the value of L_ADDR has not been changed before the next E_NWR goes high, the succeeding data will be input into the wrong latch (262), especially the preceding latch. Therefore, the original data held in the corresponding latches is lost.
Similar scenarios happened in the HWM mode. As shown in FIG. 2E, every time the data has been inputted into latch L4, the value of HWM_ADDR changes to 00 automatically with a delay time. However, if the clock signal CLK 282 comes after the new incoming E_NWR 280, the data held in latch L1 will be overwritten by the new inputted data (284), and the original data which prepares to be written into SRAM 106 is lost.
The asynchronous design for a clock signal CLK reduces the power consumption, which is suitable to small, portable electronic devices. However, in order to prevent data from being overwritten by a delayed clock signal CLK, the period for two consecutive write requests, called the cycle of writing (CYCW), is limited to be long enough. The limitation for CYCW limits the process efficiency, especially the speed for the write operation. If we can ensure that the data held in the SRAM controller won't be overwritten by succeeding the inputted data even if the clock signal CLK comes too late, the limitations for CYCW could be restricted, so that the designer may reduce the CYCW and increase the write speed.